SOI (Silicon On Insulator) substrates are known as silicon substrates in which a single crystal silicon layer is formed on a surface of an insulating layer. The formation of a device, such as a transistor, on an SOI substrate provides reduced parasitic capacitance and enhanced insulation resistance. This increases the integration density of devices and enhances the device performance. The insulating layer is formed, for example, of a silicon dioxide (SiO2) film.
In order to increase the device operating speed and further reduce the device parasitic capacitance, the single crystal silicon layer of the SOI substrate is preferably formed with a small thickness. There are known SOI substrate fabrication methods for attaining this by attaching a silicon substrate onto another substrate, such as a glass substrate, and then separating and removing part of the silicon substrate (see, for example, Non-patent Document 1).
A description is given below of an SOI substrate fabrication method involving the attachment step as described above with reference to FIGS. 24 to 27. Although the process of thinning the SOI layer can be implemented by various ways including mechanical polishing, chemical polishing and use of porous silicon, the description here is of a process using hydrogen implantation. First, as shown in FIG. 24, a surface of a silicon substrate 201, which is a first substrate, is subjected to oxidation treatment to form a silicon dioxide (SiO2) layer 202 serving as an insulating layer. Next, as shown in FIG. 25, hydrogen is ion-implanted as a peeling material through the silicon dioxide (SiO2) layer 202 into the silicon substrate 201. Thus, a hydrogen implanted layer 204 providing a release layer is formed at a fixed depth in the silicon substrate 201. Subsequently, the substrate is subjected to surface cleaning treatment, such as RCA cleaning. Then, as shown in FIG. 26, for example, a silicon substrate 203 is attached as a second substrate to the surface of the silicon dioxide layer 202. Thereafter, when the layer stack is subjected to heat treatment, microcracks are formed at the depth in the silicon substrate 201 where hydrogen ions are implanted. Thus, as shown in FIG. 27, part of the silicon substrate 201 can be separated off along the hydrogen implanted layer 204. In this manner, the silicon substrate 201 is thinned to form a silicon layer 201. After the separation, if necessary, the silicon layer 201 is thinned to a desired thickness by various methods, such as polishing or etching, and/or subjected to heat treatment to repair crystal defects produced by hydrogen implantation or smooth the silicon surface.
In the above manner, an SOI substrate is fabricated in which a SiO2 layer (insulating layer) 202 is formed on a surface of the silicon substrate (second substrate) 203 and a thin silicon layer 201 is formed on a surface of the SiO2 layer 202.
In forming a plurality of elements on a substrate, a commonly known technique for insulatively separating adjacent devices is to use a LOCOS (Local Oxidation of Silicon) process to form a selective oxide film (hereinafter, referred to as a LOCOS oxide film). A general LOCOS oxide film is fabricated by forming a patterned silicon nitride film over a silicon substrate with an oxide film therebetween and then subjecting the layer stack to oxidation to selectively form an oxide film on a region of the silicon substrate surface not covered with the silicon nitride film. During the formation of the LOCOS oxide film, silicon is consumed by an amount corresponding to approximately 45% of the thickness of the LOCOS oxide film. Therefore, the surface of the LOCOS oxide film becomes higher than the unoxidized surface of the silicon substrate by an approximately half of the thickness of the LOCOS oxide film, thereby forming a level difference.
Non-patent Document 1: Michel Bruel, “Smart-Cut: A New Silicon On Insulator Material Technology Based on Hydrogen Implantation and Wafer Bonding”, Jpn. J. Appl. Phys., Vol. 36 (1997), pp. 1636-1641
The inventors found that if a hydrogen implanted layer is formed in a semiconductor substrate having semiconductor elements, such as MOS transistors, and part of the semiconductor substrate is separated off, the semiconductor elements can be fabricated with reduced thickness on another substrate.
Generally, in methods for fabricating a semiconductor device including MOS transistors, it is desirable to reduce the number of process steps by reducing the number of masks used in order to shorten the production time and save the production cost. An exemplary known technique to attain this is to form wells for NMOS and PMOS transistors in a single photolithography process.
Consequently, it can be considered to carry out the above fabrication method found by the inventors using a single photolithography process. A description is given below of the process steps of the fabrication method with reference to FIGS. 28 to 34.
First, as shown in FIG. 28, a thermally oxidized film 102 is formed on top of a silicon substrate 101 and a silicon nitride film 103 is formed on top of the thermally oxidized film 102. Subsequently, the layer stack is subjected to a photolithography step. Specifically, the silicon nitride film 103 is patterned using a resist 104 as a mask. Thereafter, as shown in FIG. 29, an N-type impurity element 105 (for example, phosphorous) is implanted by ion implantation into an N-well forming region of the substrate that is a region thereof corresponding to an opening of the resist 104.
Thereafter, the resist 104 is removed and, as shown in FIG. 30, the silicon substrate 101 is thermally oxidized using the silicon nitride film 103 as a mask, thereby forming an oxide film 106 on top of the N-well forming region. Subsequently, as shown in FIG. 31, the silicon nitride film 103 is removed and a P-type impurity element 107 (for example, boron) is then ion-implanted into the silicon substrate 101 using the oxide film 106 as a mask. As a result, the P-type impurity element 107 is implanted into a P-well forming region of the silicon substrate 101 on which the oxide film 106 is not formed.
Next, the thermally oxidized film 102 and the oxide film 106 are removed and the silicon substrate 101 is then thermally treated in an oxidized atmosphere. Thus, as shown in FIG. 32, a thermally oxidized film 108 is formed on the substrate surface and the impurity elements 105 and 107 implanted into the N-well and P-well forming regions are diffused to form an N-well region 109 and a P-well region 110. At this time, the substrate surface is formed to have different levels: the surface of the N-well region 109 on which the oxidized film 106 had been formed is lower than the surface of the P-well region 110.
Although a detailed description is not given of the later process steps, as shown in FIG. 33, an NMOS transistor 111 and a PMOS transistor 112 are formed in the N-well region 109 and the P-well region 110, respectively.
Each of the NMOS transistor 111 and the PMOS transistor 112 includes a gate oxide film 113, a LOCOS oxide film 114, a gate electrode 115 and sidewalls 116. The NMOS transistor 111 further includes N-type high-concentration impurity regions 119 and N-type low-concentration impurity regions 120, while the PMOS transistor 112 further includes P-type high-concentration impurity regions 117 and P-type low-concentration impurity regions 118.
Subsequently, in order to form the semiconductor elements with reduced thickness on another substrate, as shown in FIG. 34, an insulating film such as SiO2 is formed over the layer stack and a planarizing film 121 is then formed on the insulating film by a planarization process, such as CMP (Chemical Mechanical Polishing). Thereafter, hydrogen is ion-implanted into the silicon substrate 101 to form a hydrogen implanted layer 122.
A description is given below of the reason why the planarizing film 121 is formed prior to the hydrogen ion implantation. If, as shown in FIG. 33, a gate electrode 115 and other parts are provided to project from the substrate surface, the substrate surface will have steep steps formed. If steep steps are formed on the substrate surface through which hydrogen is ion-implanted, a hydrogen implanted layer formed in the silicon substrate 101 will have steep steps formed in correspondence with the above steps on the substrate surface. The inventors' experiment has demonstrated that where the hydrogen implanted layer is formed to have steep steps, a region of the silicon substrate 101 cannot be well separated off along the hydrogen implanted layer during heat treatment. In particular, the region of the silicon substrate 101 to be separated off is partly left on the silicon substrate 101 at the steep steps of the hydrogen implanted layer, which makes it difficult to form the semiconductor elements with reduced thickness on another substrate.
For the above reason, in order to surely separate part of the silicon substrate 101 off from the hydrogen implanted layer, it is essential to form a planarizing film 121 to planarize the substrate surface prior to the hydrogen ion implantation. However, as shown in FIG. 34, the hydrogen implanted layer 122 is formed at a fixed depth from the surface of the planarizing film 121 but the NMOS transistor 111 and the PMOS transistor 112 are formed with a level difference between them. Therefore, when the semiconductor elements are separated at the hydrogen implanted layer 122 and formed with thus reduced thickness on another substrate, the thickness a of the silicon layer of the PMOS transistor 112 is different from the thickness b of the silicon layer of the NMOS transistor 111.
The thickness of the silicon layer has a significant effect on electrical properties of the transistors, such as parasitic capacitance, switching voltage threshold value and subthreshold characteristics. Therefore, if, as above, the NMOS transistor 111 and the PMOS transistor 112 have different silicon layer thicknesses, their electrical properties are unbalanced and their silicon layer thicknesses become hard to control.
Furthermore, for full-depletion SOI transistors, it is necessary to restrict the thickness of the silicon layer within the range from 50 to 100 nm, both inclusive. If the silicon layers of the NMOS transistor 111 and the PMOS transistor 112 have different thicknesses as mentioned above, the silicon layer of one of these transistors may be thicker or thinner than that of the other transistor by adjusting the thickness of the silicon layer of the other transistor to 50 to 100 nm. This causes a problem that the silicon layers of both the NMOS transistor 111 and the PMOS transistor 112 cannot be formed to have appropriate thicknesses.
The example embodiment presented herein has been made in view of the foregoing points and, therefore, a feature is to form a plurality of element forming surfaces of different heights on a semiconductor layer in which a release layer is to be formed and form semiconductor elements, one on each of the element forming surfaces, thereby forming associated portions of the semiconductor layer in the semiconductor elements with the same thickness.